vertex - Parses and processes Verilog HDL files

vertex [VERILOGFILE]... [option]...

Parses Verilog HDL files for use by other tools. The Verilog grammar used is 1364-1995.

-h[elp]

Prints out help screen.

-emitmono fname

Emit monolithic (parser view of) file to fname.

-emitstems

Emit source code stems to stdout.

-emitvars

Emit source code variables to stdout.

-Dx=y

Equivalent to `define X Y in source.

+define+x=y

Equivalent to `define X Y in source.

+incdir+dirname

Add dirname to include search path.

+libext+ext

Add ext to filename when searching for files.

-pragma name

Add name (synopsys, verilint, vertex) to accepted pragmas.

-y dirname

Add directory dirname to source input path.

-yi dirname

Add directory dirname to source input path (case insensitive search).

-f filename

Insert args from filename. Does not work recursively.

The following indicates that the library extension is .v and that the include directory is the current working directory and that the library directory is also the current working directory. Stems generation is enabled to generate a stems file for use with other tools. Various compile-time defines are also defined on the command line.

vertex XYZ450AC6V1.v -emitstems -y . +incdir+. +libext+.v -DUTLB_OutputData=0 -D__PORTALS_VERILOG__

Anthony Bybell <bybell@nc.rr.com>

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